1. introduction the development board for the ata6661/ ata6662 (ATA6661-EK, ata6662-ek) is designed to give designers a quick start wi th these ics and for the prototyping and testing of new designs. the ata6661/ata6662 is a fully integrated lin transceiver complying with the lin 2.0 specificat ion. the ata6661 and ata6662 are pin and function compatible, but the ata6662 has improved emc behavior. the ic interfaces between the lin protocol handler and the physical layer, and is designed to handle the low-speed data communication in vehicles, for example, in convenience electronics. impr oved slope control on the lin bus ensures secure data communication up to 20 kbaud with a rc osc illator for the protocol handling. the bus output is capable of withstanding high voltage and complies with the 42v powernet requirements. sleep mode guarantees minimal current consumption. this document has been developed to give the user an quick start with the develop- ment board of the ata6661/ata6662. for more detailed information about the use of the ata6661/ata6662 itself, please refer to the corresponding datasheet. figure 1-1. ata6661/ata6662 development board 1.1 development board features the development board for the ata6661/ata6662 supports the following features: ? includes all components necessar y for ata6661/ata6662 operation all pins are easily accessible can be used for master or slave operation wake-up pulse via an on-board switch 24v application can be built up on the board ata6661/ ata6662 development board application note 4968a?auto?01/07
2 4968a?auto?01/07 ata6661/ata6662 development board 1.2 quick start the development board for the ata6661/ata6662 is shipped with all components necessary to start with the development of a lin slave node immediately. connecting an external 12v dc power supply be tween the terminals vbat and gnd puts the ic in the pre-normal mode. in th is mode, the inhibit pin inh w ill be switched to the vs level in order to enable an external voltage regulator (not included on the board). the lin pin is in the recessive state. please note that the communication is still inactive duri ng pre-normal mode. in order to communicate via the lin bus interface, you have to switch to normal mode by applying 5v at pin en. as rxd is an open-drain output, the necessary pu ll-up resistor can be activated by applying a +5v dc voltage, for example at pin +5v on the board. 2. hardware description in the following sections only t he normal operating conditions w ill be described. for detailed information concerning the mentioned featur es, refer to the corresponding datasheet. 2.1 power supply (vbat, +5v and gnd) the development board requires an external 5.7v to 18v dc power supply between the termi- nals vbat and gnd. the input circ uit is protected agai nst inverse-polarity with the protection diode d1, so that there is normally a difference between the vbat and vs level of approxi- mately 0.7v. the dc voltage at pin +5v is only needed when the pull-up resistor for the pin rxd is to be activated. 2.2 lin interface (lin, txd and rxd) 2.2.1 bus pin (lin) a low-side driver with internal current limitation, thermal shutdown, and an internal pull-up resistor in compliance with lin spec 2.0 is implemented. lin receiver thresholds are compati- ble to the lin protocol specification. on the board at the lin pin there is a 220-pf capacitor to ground. additionally, the two extra components (diode d2 (ll4148) in series with resistor r3 (1 k ? )) necessary to use the devel- opment board for a lin master application have designated placeholders for convenient mounting. 2.2.2 input pin (txd) this pin is the microcontroller interface to c ontrol the state of the lin output. txd must be pulled to ground in order to have the lin bus low. if txd is high, the lin output transistor is turned off and the bus is in the recessive state, pulled up by the internal resistor. if txd is low, the lin output transistor is turned on and the bus is in the dominant state. an internal timer prevents the bus line from being driven permanently in the dominant state. if txd is forced to low longer than t dom > 20 ms, the lin bus driver is switched to the recessive state.
3 4968a?auto?01/07 ata6661/ata6662 development board 2.2.3 output pin (rxd) this pin reports the state of the lin bus to the microcontroller. lin high (recessive state) is reported by a high level at rxd, lin low (dominant state) is reported by a low level at rxd. the output is short-circuit protected. please note that the ata6661/ata6662 has to be in normal mode in order to have the com- munication via lin enabled. 2.3 system control (en, inh and wake) 2.3.1 enable pin (en) this pin controls the operation mode of the interface. if en = 1 the interface is in normal mode, with transmission paths from txd to lin and from lin to rxd both active. if en = 0 the device is switched to sleep mode and no transmission is possible. 2.3.2 inhibit pin (inh) this pin is used to control an external switchable voltage regulator having an inhibit input. the inhibit pin is a high-side switch structure connecte d to vs. if the device is in normal mode, the inhibit high-side switch is turned on and the exter nal voltage regulator is activated. when the device is in sleep mode, the inhibit switch is turned off and the external voltage regulator will be disabled. 2.3.3 wake pin (wake) this pin is a high voltage input used to wake the device up from sleep mode. it is usually con- nected to an external switch in order to generate a local wake-up. if no local wake-up is needed in the application, the wake pin should be connected directly to the vs pin.
4 4968a?auto?01/07 ata6661/ata6662 development board 3. schematic and layout of the at a6661/ata6662 development board figure 3-1. schematic of the development board for the ata6661/ata6662 notes: 1. d2 and r3 are only necessary for a master node. 2. r5 and d3 are only used in 24v applications. they guarantee that the supply voltage vs never exceeds the maximum rating of vs max = 40v. refer to the corresponding application note of the ata6661 for further information. 33 k ? 220 pf c2 100 nf c4 100 nf vbat gnd +5v rxd lin txd wake inh en c3 22 f/50v c1 r4 inh x1 x2 x3 0 r5b 10 k ? r1 4.7 k ? r2 ll4148 d2 1 k ? r3 bzg04-33 d3 ll4148 d1 ata6661/ ata6662 4 3 2 1 gnd lin vs inh ATA6661-EK revision 3.0 ata6662-ek inh txd wake wake switch en rxd 5 6 7 8 + 100 ? /1w r5 s1
5 4968a?auto?01/07 ata6661/ata6662 development board figure 3-2. board component placement; top side, top view figure 3-3. ata6661/ata6662 development board; top side, top view
6 4968a?auto?01/07 ata6661/ata6662 development board figure 3-4. ata6661/ata6662 development board; bottom side, top view (as if pcb were transparent)
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